=ADD=
=author=
Matasaru; Bogdan + Jebelean; Tudor
=title=
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
=number=
99-48
=month=
11
=year=
1999
=sponsor=
Partially supported by a PhD fellowship from the Upper Austrian Government
=url=
ftp://ftp.risc.uni-linz.ac.at/pub/techreports/1999/99-48.ps.gz
=abstract=
We present the FPGA implementation of an extension of the binary
{\em plus--minus} systolic algorithm which computes the GCD (greatest
common divisor) and also the normal form of a rational number,
without using division.
A sample array for 8 bit operands consumes 83.4\% of an Atmel 40K10 chip
and operates at 25 MHz.
=keywords=
systolic array, rational normalization
=howpublished=
Submitted to FPLA 2000, Villach, Austria
=location=
2
=owner=
2
=source=
3
=reftype=
14